Flip-Chip Technology on Organic Pin Grid Array Packages

As microelectronic devices become more integrated with increased functionality and higher levels of performance, the complexity of packaging technology grows proportionally. Today’s silicon processes have enabled microprocessor designs to achieve very high clock frequencies. As a result of the increase in feature integration, high clock frequencies, and the power supply requirements of the latest generation of microprocessors, the density of interconnects between processor chip and substrate has been increased remarkably. New package substrate technologies with enhanced interconnect density are required in order to take full advantage of these silicon advancements. This has created an array of challenges in package design, substrate technology development, and assembly processes development. To provide a highly integrated and lower cost package, the Flip Chip Pin Grid Array (FCPGA) package was proposed as an innovative packaging solution [1]. This package utilizes laser-drilled blind/buried vias stacked on a PTH to ease routing and to lower the power supply loop inductance. In addition, the integration of flip-chip technology on an organic substrate helps to provide adequate signal and power supply interconnects. The FCPGA package was designed as a socketable solution. By taking advantage of the existing PGA socket infrastructure, this package helped to expedite the Original Equipment Manufacturers (OEMs) acceptance of the new package. This paper also describes the challenges encountered in the past in package design, validation, and assembly process development. Several technical challenges such as meeting the stringent impedance requirement to enable RDRAM bus ∗ Other brands and names are the property of their respective owners. functionality, the optimal pinning process to certify Surface Mounted Technology (SMT) pins, and Underfill material and process development to fulfill throughput and performance requirements were overcome. The FCPGA package not only delivered a package with high performance on a cost-effective substrate, but also intelligently reused existing assembly equipment to minimize overall packaging cost. With the success of the first-generation FCPGA package technology certification, which has been utilized in the Intel® Pentium III microprocessors, future generations of this technology will be developed that should offer great advantages for future Intel products. INTRODUCTION The need for high-density interconnects in a costeffective flip-chip package was the motivation for FCPGA technology development. This paper describes the challenges encountered during the first generation FCPGA package design, validation, assembly processes, and material development. FCPGA was designed as a socketable solution. The pin side view of an FCPGA package is shown in Figure 1. The use of the existing 370 socket infrastructure helped with the OEM acceptance of this new package. The key features of the FCPGA technology are as follows: 1. Stackup The substrate is comprised of an FR-5 equivalent core with two resin build-up layers on each side. Both blind and buried vias are used to ease package routing. 2. Bump Pitch The flip-chip interconnects are built on an organic substrate with a solder bump pitch of 11 mils (279.4 μm). Intel Technology Journal Q3, 2000 Flip-Chip Technology on Organic Pin Grid Array Packages 2 3. Decoupling Capacitors Pin side decoupling capacitors were added to lower the power supply loop inductance. 4. Surface Mount Package Pins SMT pins were used to ease package routing. This was an improvement over through hole mounted pins. The use of SnSb solder to join the package and pins provided solder joint reliability through subsequent reflow operations. Figure 1: Pin side view of the FCPGA package Package Design and Validation Overview Package Designs Several test vehicles and test structures were designed and analyzed to validate the package’s electrical, thermal, mechanical, and reliability performance. Key attributes of several packages are tabulated in Table 1 [2, 3, 4, 5]. Table 1: Package design attributes Attributes Test Package A Test Package B Test Package C Form Factor 1.95" x 1.95" 1.95" x 1.95" 1.95" x 1.95" Thickness 1.1 +/0.1 mm 1.1 +/0.1 mm 1.1 +/0.1 mm Package Layers 6 layers 6 layers 6 layers Min. Bump Pitch 279 μm 279 μm 279 μm Bump Pattern FCR in three I/O rows Square gird in core area FCR in three I/O rows Square grid in core area FCR in three I/O rows Slight offset parallelogram grid in core area # of C4 bumps 1199 1286 1209 Die Size 0.355" x 0.455" 0.440" x 0.363" 0.438" x 0.386" Die Layers short loop full loop full loop Core Voltage > 25V 1.5V / 1.6 V 1.55V / 1.8V Package Stackup L1/L2 : signal layers L3-L6 : plane layers L1 : signal layers L2, L5 : partial signal layers L3, L4, L6 plane layers L1, L2 : signal layers L3-L6 : plane layers Vias Single-layer μ-vias Two-layer μ-vias Single-layer μ-vias Single-layer μ-vias Footprint PGA_370 PGA_370 PGA_370 # of chip cap. 18 14 7 Power Dissipation > 30 W 15 ~ 28 W 15 ~ 20 W The layer structure of an FCPGA substrate is displayed in Figure 2; the targeted thickness of each layer and package key feature sizes are given in Table 2.